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How does a NAND gate work? (Very basic question)
Why doesn't current flow through the common part of a circuit?What is the voltage of Vo in this circuit without a closed loop?How does the OR gate work?If there is a branch and the two paths lead back to the same ground, will they both recieve power?How does a Miller cap physically create a pole in circuits?Detecting a connection to a distinct circuit with no current returnIs the flow of current in this RL circuit ambiguously defined?Question About Current Flow DirectionWhat's the reason for this symmetry argument?Will I be able to keep this circuit on by routing the emitter to the base?
.everyoneloves__top-leaderboard:empty,.everyoneloves__mid-leaderboard:empty,.everyoneloves__bot-mid-leaderboard:empty margin-bottom:0;
$begingroup$
I'll preface this question by saying that I am a software developer just starting to learn the basics of electronics, so it's very likely I'm missing some fundamental intuition here.
Below is a mechanical NAND gate with two switches. I think it's supposed to be obvious that when the switches are closed, the output Q is 0 rather than 1. I don't see why this is.
I see that when the two switches are closed, there is a path from V+ to ground, and that current will flow to ground. But there's also a path from V+ to Q, so won't some current still flow to the output, putting it in a 1 state?
The intuition I'm using (which may be totally wrong) is this:
- Current acts like water gushing from V+ down all available paths.
- At a junction, current will flow through both paths in an amount inversely proportional to resistance. In this case, both paths have no additional resistance so they should split the current equally.
- The boolean equivalent of a 1 is that current is flowing through a point.
Please help me understand what I'm missing! And if you can point me to a book or online resource explaining these fundamentals, that would be very helpful. I've tried looking at a lot of "circuit tutorial" content on Google, but surprisingly haven't been able to resolve my confusion here.
circuit-analysis logic-gates
edited Apr 30 at 16:23
psmears
55335
asked Apr 30 at 0:54
rampatowlrampatowl
1394
$endgroup$
add a comment |
$begingroup$
I'll preface this question by saying that I am a software developer just starting to learn the basics of electronics, so it's very likely I'm missing some fundamental intuition here.
Below is a mechanical NAND gate with two switches. I think it's supposed to be obvious that when the switches are closed, the output Q is 0 rather than 1. I don't see why this is.
I see that when the two switches are closed, there is a path from V+ to ground, and that current will flow to ground. But there's also a path from V+ to Q, so won't some current still flow to the output, putting it in a 1 state?
The intuition I'm using (which may be totally wrong) is this:
- Current acts like water gushing from V+ down all available paths.
- At a junction, current will flow through both paths in an amount inversely proportional to resistance. In this case, both paths have no additional resistance so they should split the current equally.
- The boolean equivalent of a 1 is that current is flowing through a point.
Please help me understand what I'm missing! And if you can point me to a book or online resource explaining these fundamentals, that would be very helpful. I've tried looking at a lot of "circuit tutorial" content on Google, but surprisingly haven't been able to resolve my confusion here.
circuit-analysis logic-gates
edited Apr 30 at 16:23
psmears
55335
asked Apr 30 at 0:54
rampatowlrampatowl
1394
$endgroup$
$begingroup$
The source impedance of the switch is 0 while in normal logic it is <=50 Ohms so the load impedance being much higher permits many loads to applied without significant change in voltage. For TTL, the limit was 10 units of load. But for static CMOS , the limit depends on the equivalent input capacitance and current limit of the switch as this affects rise/fall time. T=RC
$endgroup$
– Sunnyskyguy EE75
Apr 30 at 1:02
$begingroup$
"I see that when the two switches are closed, there is a path from V+ to ground, and that current will flow to ground. But there's also a path from V+ to Q,". No, there is only 1 path, V+ to ground, Q is a point on that path. And, when the switches are closed, Q is at the same potential as ground.
$endgroup$
– Glen Yates
Apr 30 at 15:13
add a comment |
$begingroup$
I'll preface this question by saying that I am a software developer just starting to learn the basics of electronics, so it's very likely I'm missing some fundamental intuition here.
Below is a mechanical NAND gate with two switches. I think it's supposed to be obvious that when the switches are closed, the output Q is 0 rather than 1. I don't see why this is.
I see that when the two switches are closed, there is a path from V+ to ground, and that current will flow to ground. But there's also a path from V+ to Q, so won't some current still flow to the output, putting it in a 1 state?
The intuition I'm using (which may be totally wrong) is this:
- Current acts like water gushing from V+ down all available paths.
- At a junction, current will flow through both paths in an amount inversely proportional to resistance. In this case, both paths have no additional resistance so they should split the current equally.
- The boolean equivalent of a 1 is that current is flowing through a point.
Please help me understand what I'm missing! And if you can point me to a book or online resource explaining these fundamentals, that would be very helpful. I've tried looking at a lot of "circuit tutorial" content on Google, but surprisingly haven't been able to resolve my confusion here.
circuit-analysis logic-gates
edited Apr 30 at 16:23
psmears
55335
asked Apr 30 at 0:54
rampatowlrampatowl
1394
$endgroup$
I'll preface this question by saying that I am a software developer just starting to learn the basics of electronics, so it's very likely I'm missing some fundamental intuition here.
Below is a mechanical NAND gate with two switches. I think it's supposed to be obvious that when the switches are closed, the output Q is 0 rather than 1. I don't see why this is.
I see that when the two switches are closed, there is a path from V+ to ground, and that current will flow to ground. But there's also a path from V+ to Q, so won't some current still flow to the output, putting it in a 1 state?
The intuition I'm using (which may be totally wrong) is this:
- Current acts like water gushing from V+ down all available paths.
- At a junction, current will flow through both paths in an amount inversely proportional to resistance. In this case, both paths have no additional resistance so they should split the current equally.
- The boolean equivalent of a 1 is that current is flowing through a point.
Please help me understand what I'm missing! And if you can point me to a book or online resource explaining these fundamentals, that would be very helpful. I've tried looking at a lot of "circuit tutorial" content on Google, but surprisingly haven't been able to resolve my confusion here.
circuit-analysis logic-gates
circuit-analysis logic-gates
edited Apr 30 at 16:23
psmears
55335
asked Apr 30 at 0:54
rampatowlrampatowl
1394
edited Apr 30 at 16:23
psmears
55335
asked Apr 30 at 0:54
rampatowlrampatowl
1394
edited Apr 30 at 16:23
psmears
55335
edited Apr 30 at 16:23
psmears
55335
edited Apr 30 at 16:23
psmears
55335
55335
asked Apr 30 at 0:54
rampatowlrampatowl
1394
asked Apr 30 at 0:54
rampatowlrampatowl
1394
asked Apr 30 at 0:54
rampatowlrampatowl
1394
1394
$begingroup$
The source impedance of the switch is 0 while in normal logic it is <=50 Ohms so the load impedance being much higher permits many loads to applied without significant change in voltage. For TTL, the limit was 10 units of load. But for static CMOS , the limit depends on the equivalent input capacitance and current limit of the switch as this affects rise/fall time. T=RC
$endgroup$
– Sunnyskyguy EE75
Apr 30 at 1:02
$begingroup$
"I see that when the two switches are closed, there is a path from V+ to ground, and that current will flow to ground. But there's also a path from V+ to Q,". No, there is only 1 path, V+ to ground, Q is a point on that path. And, when the switches are closed, Q is at the same potential as ground.
$endgroup$
– Glen Yates
Apr 30 at 15:13
add a comment |
$begingroup$
The source impedance of the switch is 0 while in normal logic it is <=50 Ohms so the load impedance being much higher permits many loads to applied without significant change in voltage. For TTL, the limit was 10 units of load. But for static CMOS , the limit depends on the equivalent input capacitance and current limit of the switch as this affects rise/fall time. T=RC
$endgroup$
– Sunnyskyguy EE75
Apr 30 at 1:02
$begingroup$
"I see that when the two switches are closed, there is a path from V+ to ground, and that current will flow to ground. But there's also a path from V+ to Q,". No, there is only 1 path, V+ to ground, Q is a point on that path. And, when the switches are closed, Q is at the same potential as ground.
$endgroup$
– Glen Yates
Apr 30 at 15:13
$begingroup$
The source impedance of the switch is 0 while in normal logic it is <=50 Ohms so the load impedance being much higher permits many loads to applied without significant change in voltage. For TTL, the limit was 10 units of load. But for static CMOS , the limit depends on the equivalent input capacitance and current limit of the switch as this affects rise/fall time. T=RC
$endgroup$
– Sunnyskyguy EE75
Apr 30 at 1:02
$begingroup$
The source impedance of the switch is 0 while in normal logic it is <=50 Ohms so the load impedance being much higher permits many loads to applied without significant change in voltage. For TTL, the limit was 10 units of load. But for static CMOS , the limit depends on the equivalent input capacitance and current limit of the switch as this affects rise/fall time. T=RC
$endgroup$
– Sunnyskyguy EE75
Apr 30 at 1:02
$begingroup$
"I see that when the two switches are closed, there is a path from V+ to ground, and that current will flow to ground. But there's also a path from V+ to Q,". No, there is only 1 path, V+ to ground, Q is a point on that path. And, when the switches are closed, Q is at the same potential as ground.
$endgroup$
– Glen Yates
Apr 30 at 15:13
$begingroup$
"I see that when the two switches are closed, there is a path from V+ to ground, and that current will flow to ground. But there's also a path from V+ to Q,". No, there is only 1 path, V+ to ground, Q is a point on that path. And, when the switches are closed, Q is at the same potential as ground.
$endgroup$
– Glen Yates
Apr 30 at 15:13
add a comment |
5 Answers
5
active
oldest
votes
$begingroup$
The boolean equivalent of a 1 is that current is flowing through a point.
That's the fundamental confusion leading to difficulty in understanding the circuit.
Single ended logic like this encodes state as voltage not current.
Inputs of logic gates are designed to source or sink very little current, so the output of the previous stage is easily able to impose its intended voltage on the connection between output and the following input with very little current needing to flow.
Current-mode signaling does exist, but it's generally used only in noisy situations, for example the time-tested 4-20 mA current loop standard.
answered Apr 30 at 0:59
Chris StrattonChris Stratton
24.1k22968
$endgroup$
$begingroup$
Gotcha. Can you explain why the voltage of Q is only positive when there is no path from V+ to ground?
$endgroup$
– rampatowl
Apr 30 at 1:34
2
$begingroup$
Because in a "tug of war" the low resistance switches win over the pulling resistor in imposing the voltage on their far side.
$endgroup$
– Chris Stratton
Apr 30 at 1:46
$begingroup$
Oh of course! So is the rule something like: to determine whether an input pin is high or low, look at every defined component it is connected to, and it will take on the value of the defined component with the least resistance along the path to that component?
$endgroup$
– rampatowl
Apr 30 at 1:56
3
$begingroup$
Approximately: but not just the components but what is behind them, in this case "stiff" voltage rails. And if the difference in resistances is not drastic then the voltage may end up intermediate.
$endgroup$
– Chris Stratton
Apr 30 at 2:02
add a comment |
$begingroup$
First off the "N" means that it inverts the input the schematic is sort of doing the same but it gets off track of how the gates work. If you drew it with a relay it would make more sense
simulate this circuit – Schematic created using CircuitLab
You need to study pull down and pull up resistors, the value of the resistor limits the voltage, current is not an issue really because this is all at "logic level". I had a hard time with the logic stuff at first and then all of a sudden it all made sense, good luck my friend.
answered Apr 30 at 1:34
vaporlockvaporlock
313
$endgroup$
add a comment |
$begingroup$
I also had this problem since I started learning a bit about electronics (I'm also a software engineer).
Electricity always wants to balance. If there is GND, all electricity will flow to there (actually the electrons move in reverse direction but let's ignore that for now).
This means if the switches are closed, and if Q > 0 V, all electricity will flow to GND, meaning Q will be 0 V in a very short time (read: almost instantly).
However, when one of the switches is open, the voltage from V+ will flow to Q if Q has less voltage than V+ (which is likely so), so Q will end up having the same voltage as V+.
answered Apr 30 at 1:02
Michel KeijzersMichel Keijzers
7,34093373
$endgroup$
add a comment |
$begingroup$
It is indeed a basic question but I think it is a very valid one. I am an electrical engineer and agree that it seems that the logic is broken but read on and you'll see how easy it is.
As it was answered before, electronic logic gates are named for its voltage behavior, but that's the easy part. Whenever both SW1 and SW2 are pressed (i.e. its value is "1"), the voltage in the point Q is "0". We can translate it to using logic gate symbols.
simulate this circuit – Schematic created using CircuitLab
The voltage at Q (i.e. Q to GND) is *Logic 0" when both buttons are pressed.
Now comes the not complicated but rather confusing part. Suppose you have the following circuit:
simulate this circuit
I'm sure you will say that's definitively an AND. But let's keep in mind the fact that the point Q voltage drops to 0 when both buttons are pressed and let's translate the circuit to using logic gates.
simulate this circuit
Now, you will see that the relay will turn on only when the point Q voltage drops to zero (i.e. when both buttons are pressed.) So, think it this way; if you were going to do your own physical implementation of this circuit with logic gates, you would have to buy a NAND. Now you have a Wired AND despite the fact that you are actually using a NAND gate. So don't worry, your computational logic is safe.
answered Apr 30 at 11:11
KraussKrauss
268111
$endgroup$
add a comment |
$begingroup$
I found very useful the simple description of a NAND gate to act thusly
"any zero in causes a one out". This circuit will do that.
In this circuit, if either switch is pressed, which causes a ZERO volts input to the inverter, then a logic HIGH appears out of the circuit.
Note we mixed logic 1 and logic HIGH and VDD and TRUE, along with logic 0 and FALSE and GROUND and logic LOW.
simulate this circuit – Schematic created using CircuitLab
answered Apr 30 at 2:26
analogsystemsrfanalogsystemsrf
16.7k2823
$endgroup$
2
$begingroup$
Looks like an 'OR' gate to me... but maybe I just don't understand how you intend for those switches to work (that's a problem with your answer -- you didn't even try to describe their behavior)
$endgroup$
– Ben Voigt
Apr 30 at 3:18
add a comment |
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5 Answers
5
active
oldest
votes
5 Answers
5
active
oldest
votes
active
oldest
votes
active
oldest
votes
$begingroup$
The boolean equivalent of a 1 is that current is flowing through a point.
That's the fundamental confusion leading to difficulty in understanding the circuit.
Single ended logic like this encodes state as voltage not current.
Inputs of logic gates are designed to source or sink very little current, so the output of the previous stage is easily able to impose its intended voltage on the connection between output and the following input with very little current needing to flow.
Current-mode signaling does exist, but it's generally used only in noisy situations, for example the time-tested 4-20 mA current loop standard.
answered Apr 30 at 0:59
Chris StrattonChris Stratton
24.1k22968
$endgroup$
$begingroup$
Gotcha. Can you explain why the voltage of Q is only positive when there is no path from V+ to ground?
$endgroup$
– rampatowl
Apr 30 at 1:34
2
$begingroup$
Because in a "tug of war" the low resistance switches win over the pulling resistor in imposing the voltage on their far side.
$endgroup$
– Chris Stratton
Apr 30 at 1:46
$begingroup$
Oh of course! So is the rule something like: to determine whether an input pin is high or low, look at every defined component it is connected to, and it will take on the value of the defined component with the least resistance along the path to that component?
$endgroup$
– rampatowl
Apr 30 at 1:56
3
$begingroup$
Approximately: but not just the components but what is behind them, in this case "stiff" voltage rails. And if the difference in resistances is not drastic then the voltage may end up intermediate.
$endgroup$
– Chris Stratton
Apr 30 at 2:02
add a comment |
$begingroup$
The boolean equivalent of a 1 is that current is flowing through a point.
That's the fundamental confusion leading to difficulty in understanding the circuit.
Single ended logic like this encodes state as voltage not current.
Inputs of logic gates are designed to source or sink very little current, so the output of the previous stage is easily able to impose its intended voltage on the connection between output and the following input with very little current needing to flow.
Current-mode signaling does exist, but it's generally used only in noisy situations, for example the time-tested 4-20 mA current loop standard.
answered Apr 30 at 0:59
Chris StrattonChris Stratton
24.1k22968
$endgroup$
$begingroup$
Gotcha. Can you explain why the voltage of Q is only positive when there is no path from V+ to ground?
$endgroup$
– rampatowl
Apr 30 at 1:34
2
$begingroup$
Because in a "tug of war" the low resistance switches win over the pulling resistor in imposing the voltage on their far side.
$endgroup$
– Chris Stratton
Apr 30 at 1:46
$begingroup$
Oh of course! So is the rule something like: to determine whether an input pin is high or low, look at every defined component it is connected to, and it will take on the value of the defined component with the least resistance along the path to that component?
$endgroup$
– rampatowl
Apr 30 at 1:56
3
$begingroup$
Approximately: but not just the components but what is behind them, in this case "stiff" voltage rails. And if the difference in resistances is not drastic then the voltage may end up intermediate.
$endgroup$
– Chris Stratton
Apr 30 at 2:02
add a comment |
$begingroup$
The boolean equivalent of a 1 is that current is flowing through a point.
That's the fundamental confusion leading to difficulty in understanding the circuit.
Single ended logic like this encodes state as voltage not current.
Inputs of logic gates are designed to source or sink very little current, so the output of the previous stage is easily able to impose its intended voltage on the connection between output and the following input with very little current needing to flow.
Current-mode signaling does exist, but it's generally used only in noisy situations, for example the time-tested 4-20 mA current loop standard.
answered Apr 30 at 0:59
Chris StrattonChris Stratton
24.1k22968
$endgroup$
The boolean equivalent of a 1 is that current is flowing through a point.
That's the fundamental confusion leading to difficulty in understanding the circuit.
Single ended logic like this encodes state as voltage not current.
Inputs of logic gates are designed to source or sink very little current, so the output of the previous stage is easily able to impose its intended voltage on the connection between output and the following input with very little current needing to flow.
Current-mode signaling does exist, but it's generally used only in noisy situations, for example the time-tested 4-20 mA current loop standard.
answered Apr 30 at 0:59
Chris StrattonChris Stratton
24.1k22968
edited Apr 30 at 1:04
answered Apr 30 at 0:59
Chris StrattonChris Stratton
24.1k22968
answered Apr 30 at 0:59
Chris StrattonChris Stratton
24.1k22968
answered Apr 30 at 0:59
Chris StrattonChris Stratton
24.1k22968
24.1k22968
$begingroup$
Gotcha. Can you explain why the voltage of Q is only positive when there is no path from V+ to ground?
$endgroup$
– rampatowl
Apr 30 at 1:34
2
$begingroup$
Because in a "tug of war" the low resistance switches win over the pulling resistor in imposing the voltage on their far side.
$endgroup$
– Chris Stratton
Apr 30 at 1:46
$begingroup$
Oh of course! So is the rule something like: to determine whether an input pin is high or low, look at every defined component it is connected to, and it will take on the value of the defined component with the least resistance along the path to that component?
$endgroup$
– rampatowl
Apr 30 at 1:56
3
$begingroup$
Approximately: but not just the components but what is behind them, in this case "stiff" voltage rails. And if the difference in resistances is not drastic then the voltage may end up intermediate.
$endgroup$
– Chris Stratton
Apr 30 at 2:02
add a comment |
$begingroup$
Gotcha. Can you explain why the voltage of Q is only positive when there is no path from V+ to ground?
$endgroup$
– rampatowl
Apr 30 at 1:34
2
$begingroup$
Because in a "tug of war" the low resistance switches win over the pulling resistor in imposing the voltage on their far side.
$endgroup$
– Chris Stratton
Apr 30 at 1:46
$begingroup$
Oh of course! So is the rule something like: to determine whether an input pin is high or low, look at every defined component it is connected to, and it will take on the value of the defined component with the least resistance along the path to that component?
$endgroup$
– rampatowl
Apr 30 at 1:56
3
$begingroup$
Approximately: but not just the components but what is behind them, in this case "stiff" voltage rails. And if the difference in resistances is not drastic then the voltage may end up intermediate.
$endgroup$
– Chris Stratton
Apr 30 at 2:02
$begingroup$
Gotcha. Can you explain why the voltage of Q is only positive when there is no path from V+ to ground?
$endgroup$
– rampatowl
Apr 30 at 1:34
$begingroup$
Gotcha. Can you explain why the voltage of Q is only positive when there is no path from V+ to ground?
$endgroup$
– rampatowl
Apr 30 at 1:34
2
2
$begingroup$
Because in a "tug of war" the low resistance switches win over the pulling resistor in imposing the voltage on their far side.
$endgroup$
– Chris Stratton
Apr 30 at 1:46
$begingroup$
Because in a "tug of war" the low resistance switches win over the pulling resistor in imposing the voltage on their far side.
$endgroup$
– Chris Stratton
Apr 30 at 1:46
$begingroup$
Oh of course! So is the rule something like: to determine whether an input pin is high or low, look at every defined component it is connected to, and it will take on the value of the defined component with the least resistance along the path to that component?
$endgroup$
– rampatowl
Apr 30 at 1:56
$begingroup$
Oh of course! So is the rule something like: to determine whether an input pin is high or low, look at every defined component it is connected to, and it will take on the value of the defined component with the least resistance along the path to that component?
$endgroup$
– rampatowl
Apr 30 at 1:56
3
3
$begingroup$
Approximately: but not just the components but what is behind them, in this case "stiff" voltage rails. And if the difference in resistances is not drastic then the voltage may end up intermediate.
$endgroup$
– Chris Stratton
Apr 30 at 2:02
$begingroup$
Approximately: but not just the components but what is behind them, in this case "stiff" voltage rails. And if the difference in resistances is not drastic then the voltage may end up intermediate.
$endgroup$
– Chris Stratton
Apr 30 at 2:02
add a comment |
$begingroup$
First off the "N" means that it inverts the input the schematic is sort of doing the same but it gets off track of how the gates work. If you drew it with a relay it would make more sense
simulate this circuit – Schematic created using CircuitLab
You need to study pull down and pull up resistors, the value of the resistor limits the voltage, current is not an issue really because this is all at "logic level". I had a hard time with the logic stuff at first and then all of a sudden it all made sense, good luck my friend.
answered Apr 30 at 1:34
vaporlockvaporlock
313
$endgroup$
add a comment |
$begingroup$
First off the "N" means that it inverts the input the schematic is sort of doing the same but it gets off track of how the gates work. If you drew it with a relay it would make more sense
simulate this circuit – Schematic created using CircuitLab
You need to study pull down and pull up resistors, the value of the resistor limits the voltage, current is not an issue really because this is all at "logic level". I had a hard time with the logic stuff at first and then all of a sudden it all made sense, good luck my friend.
answered Apr 30 at 1:34
vaporlockvaporlock
313
$endgroup$
add a comment |
$begingroup$
First off the "N" means that it inverts the input the schematic is sort of doing the same but it gets off track of how the gates work. If you drew it with a relay it would make more sense
simulate this circuit – Schematic created using CircuitLab
You need to study pull down and pull up resistors, the value of the resistor limits the voltage, current is not an issue really because this is all at "logic level". I had a hard time with the logic stuff at first and then all of a sudden it all made sense, good luck my friend.
answered Apr 30 at 1:34
vaporlockvaporlock
313
$endgroup$
First off the "N" means that it inverts the input the schematic is sort of doing the same but it gets off track of how the gates work. If you drew it with a relay it would make more sense
simulate this circuit – Schematic created using CircuitLab
You need to study pull down and pull up resistors, the value of the resistor limits the voltage, current is not an issue really because this is all at "logic level". I had a hard time with the logic stuff at first and then all of a sudden it all made sense, good luck my friend.
answered Apr 30 at 1:34
vaporlockvaporlock
313
edited Apr 30 at 1:50
answered Apr 30 at 1:34
vaporlockvaporlock
313
answered Apr 30 at 1:34
vaporlockvaporlock
313
answered Apr 30 at 1:34
vaporlockvaporlock
313
313
add a comment |
add a comment |
$begingroup$
I also had this problem since I started learning a bit about electronics (I'm also a software engineer).
Electricity always wants to balance. If there is GND, all electricity will flow to there (actually the electrons move in reverse direction but let's ignore that for now).
This means if the switches are closed, and if Q > 0 V, all electricity will flow to GND, meaning Q will be 0 V in a very short time (read: almost instantly).
However, when one of the switches is open, the voltage from V+ will flow to Q if Q has less voltage than V+ (which is likely so), so Q will end up having the same voltage as V+.
answered Apr 30 at 1:02
Michel KeijzersMichel Keijzers
7,34093373
$endgroup$
add a comment |
$begingroup$
I also had this problem since I started learning a bit about electronics (I'm also a software engineer).
Electricity always wants to balance. If there is GND, all electricity will flow to there (actually the electrons move in reverse direction but let's ignore that for now).
This means if the switches are closed, and if Q > 0 V, all electricity will flow to GND, meaning Q will be 0 V in a very short time (read: almost instantly).
However, when one of the switches is open, the voltage from V+ will flow to Q if Q has less voltage than V+ (which is likely so), so Q will end up having the same voltage as V+.
answered Apr 30 at 1:02
Michel KeijzersMichel Keijzers
7,34093373
$endgroup$
add a comment |
$begingroup$
I also had this problem since I started learning a bit about electronics (I'm also a software engineer).
Electricity always wants to balance. If there is GND, all electricity will flow to there (actually the electrons move in reverse direction but let's ignore that for now).
This means if the switches are closed, and if Q > 0 V, all electricity will flow to GND, meaning Q will be 0 V in a very short time (read: almost instantly).
However, when one of the switches is open, the voltage from V+ will flow to Q if Q has less voltage than V+ (which is likely so), so Q will end up having the same voltage as V+.
answered Apr 30 at 1:02
Michel KeijzersMichel Keijzers
7,34093373
$endgroup$
I also had this problem since I started learning a bit about electronics (I'm also a software engineer).
Electricity always wants to balance. If there is GND, all electricity will flow to there (actually the electrons move in reverse direction but let's ignore that for now).
This means if the switches are closed, and if Q > 0 V, all electricity will flow to GND, meaning Q will be 0 V in a very short time (read: almost instantly).
However, when one of the switches is open, the voltage from V+ will flow to Q if Q has less voltage than V+ (which is likely so), so Q will end up having the same voltage as V+.
answered Apr 30 at 1:02
Michel KeijzersMichel Keijzers
7,34093373
answered Apr 30 at 1:02
Michel KeijzersMichel Keijzers
7,34093373
answered Apr 30 at 1:02
Michel KeijzersMichel Keijzers
7,34093373
answered Apr 30 at 1:02
Michel KeijzersMichel Keijzers
7,34093373
7,34093373
add a comment |
add a comment |
$begingroup$
It is indeed a basic question but I think it is a very valid one. I am an electrical engineer and agree that it seems that the logic is broken but read on and you'll see how easy it is.
As it was answered before, electronic logic gates are named for its voltage behavior, but that's the easy part. Whenever both SW1 and SW2 are pressed (i.e. its value is "1"), the voltage in the point Q is "0". We can translate it to using logic gate symbols.
simulate this circuit – Schematic created using CircuitLab
The voltage at Q (i.e. Q to GND) is *Logic 0" when both buttons are pressed.
Now comes the not complicated but rather confusing part. Suppose you have the following circuit:
simulate this circuit
I'm sure you will say that's definitively an AND. But let's keep in mind the fact that the point Q voltage drops to 0 when both buttons are pressed and let's translate the circuit to using logic gates.
simulate this circuit
Now, you will see that the relay will turn on only when the point Q voltage drops to zero (i.e. when both buttons are pressed.) So, think it this way; if you were going to do your own physical implementation of this circuit with logic gates, you would have to buy a NAND. Now you have a Wired AND despite the fact that you are actually using a NAND gate. So don't worry, your computational logic is safe.
answered Apr 30 at 11:11
KraussKrauss
268111
$endgroup$
add a comment |
$begingroup$
It is indeed a basic question but I think it is a very valid one. I am an electrical engineer and agree that it seems that the logic is broken but read on and you'll see how easy it is.
As it was answered before, electronic logic gates are named for its voltage behavior, but that's the easy part. Whenever both SW1 and SW2 are pressed (i.e. its value is "1"), the voltage in the point Q is "0". We can translate it to using logic gate symbols.
simulate this circuit – Schematic created using CircuitLab
The voltage at Q (i.e. Q to GND) is *Logic 0" when both buttons are pressed.
Now comes the not complicated but rather confusing part. Suppose you have the following circuit:
simulate this circuit
I'm sure you will say that's definitively an AND. But let's keep in mind the fact that the point Q voltage drops to 0 when both buttons are pressed and let's translate the circuit to using logic gates.
simulate this circuit
Now, you will see that the relay will turn on only when the point Q voltage drops to zero (i.e. when both buttons are pressed.) So, think it this way; if you were going to do your own physical implementation of this circuit with logic gates, you would have to buy a NAND. Now you have a Wired AND despite the fact that you are actually using a NAND gate. So don't worry, your computational logic is safe.
answered Apr 30 at 11:11
KraussKrauss
268111
$endgroup$
add a comment |
$begingroup$
It is indeed a basic question but I think it is a very valid one. I am an electrical engineer and agree that it seems that the logic is broken but read on and you'll see how easy it is.
As it was answered before, electronic logic gates are named for its voltage behavior, but that's the easy part. Whenever both SW1 and SW2 are pressed (i.e. its value is "1"), the voltage in the point Q is "0". We can translate it to using logic gate symbols.
simulate this circuit – Schematic created using CircuitLab
The voltage at Q (i.e. Q to GND) is *Logic 0" when both buttons are pressed.
Now comes the not complicated but rather confusing part. Suppose you have the following circuit:
simulate this circuit
I'm sure you will say that's definitively an AND. But let's keep in mind the fact that the point Q voltage drops to 0 when both buttons are pressed and let's translate the circuit to using logic gates.
simulate this circuit
Now, you will see that the relay will turn on only when the point Q voltage drops to zero (i.e. when both buttons are pressed.) So, think it this way; if you were going to do your own physical implementation of this circuit with logic gates, you would have to buy a NAND. Now you have a Wired AND despite the fact that you are actually using a NAND gate. So don't worry, your computational logic is safe.
answered Apr 30 at 11:11
KraussKrauss
268111
$endgroup$
It is indeed a basic question but I think it is a very valid one. I am an electrical engineer and agree that it seems that the logic is broken but read on and you'll see how easy it is.
As it was answered before, electronic logic gates are named for its voltage behavior, but that's the easy part. Whenever both SW1 and SW2 are pressed (i.e. its value is "1"), the voltage in the point Q is "0". We can translate it to using logic gate symbols.
simulate this circuit – Schematic created using CircuitLab
The voltage at Q (i.e. Q to GND) is *Logic 0" when both buttons are pressed.
Now comes the not complicated but rather confusing part. Suppose you have the following circuit:
simulate this circuit
I'm sure you will say that's definitively an AND. But let's keep in mind the fact that the point Q voltage drops to 0 when both buttons are pressed and let's translate the circuit to using logic gates.
simulate this circuit
Now, you will see that the relay will turn on only when the point Q voltage drops to zero (i.e. when both buttons are pressed.) So, think it this way; if you were going to do your own physical implementation of this circuit with logic gates, you would have to buy a NAND. Now you have a Wired AND despite the fact that you are actually using a NAND gate. So don't worry, your computational logic is safe.
answered Apr 30 at 11:11
KraussKrauss
268111
answered Apr 30 at 11:11
KraussKrauss
268111
answered Apr 30 at 11:11
KraussKrauss
268111
answered Apr 30 at 11:11
KraussKrauss
268111
268111
add a comment |
add a comment |
$begingroup$
I found very useful the simple description of a NAND gate to act thusly
"any zero in causes a one out". This circuit will do that.
In this circuit, if either switch is pressed, which causes a ZERO volts input to the inverter, then a logic HIGH appears out of the circuit.
Note we mixed logic 1 and logic HIGH and VDD and TRUE, along with logic 0 and FALSE and GROUND and logic LOW.
simulate this circuit – Schematic created using CircuitLab
answered Apr 30 at 2:26
analogsystemsrfanalogsystemsrf
16.7k2823
$endgroup$
2
$begingroup$
Looks like an 'OR' gate to me... but maybe I just don't understand how you intend for those switches to work (that's a problem with your answer -- you didn't even try to describe their behavior)
$endgroup$
– Ben Voigt
Apr 30 at 3:18
add a comment |
$begingroup$
I found very useful the simple description of a NAND gate to act thusly
"any zero in causes a one out". This circuit will do that.
In this circuit, if either switch is pressed, which causes a ZERO volts input to the inverter, then a logic HIGH appears out of the circuit.
Note we mixed logic 1 and logic HIGH and VDD and TRUE, along with logic 0 and FALSE and GROUND and logic LOW.
simulate this circuit – Schematic created using CircuitLab
answered Apr 30 at 2:26
analogsystemsrfanalogsystemsrf
16.7k2823
$endgroup$
2
$begingroup$
Looks like an 'OR' gate to me... but maybe I just don't understand how you intend for those switches to work (that's a problem with your answer -- you didn't even try to describe their behavior)
$endgroup$
– Ben Voigt
Apr 30 at 3:18
add a comment |
$begingroup$
I found very useful the simple description of a NAND gate to act thusly
"any zero in causes a one out". This circuit will do that.
In this circuit, if either switch is pressed, which causes a ZERO volts input to the inverter, then a logic HIGH appears out of the circuit.
Note we mixed logic 1 and logic HIGH and VDD and TRUE, along with logic 0 and FALSE and GROUND and logic LOW.
simulate this circuit – Schematic created using CircuitLab
answered Apr 30 at 2:26
analogsystemsrfanalogsystemsrf
16.7k2823
$endgroup$
I found very useful the simple description of a NAND gate to act thusly
"any zero in causes a one out". This circuit will do that.
In this circuit, if either switch is pressed, which causes a ZERO volts input to the inverter, then a logic HIGH appears out of the circuit.
Note we mixed logic 1 and logic HIGH and VDD and TRUE, along with logic 0 and FALSE and GROUND and logic LOW.
simulate this circuit – Schematic created using CircuitLab
answered Apr 30 at 2:26
analogsystemsrfanalogsystemsrf
16.7k2823
edited Apr 30 at 13:13
answered Apr 30 at 2:26
analogsystemsrfanalogsystemsrf
16.7k2823
answered Apr 30 at 2:26
analogsystemsrfanalogsystemsrf
16.7k2823
answered Apr 30 at 2:26
analogsystemsrfanalogsystemsrf
16.7k2823
16.7k2823
2
$begingroup$
Looks like an 'OR' gate to me... but maybe I just don't understand how you intend for those switches to work (that's a problem with your answer -- you didn't even try to describe their behavior)
$endgroup$
– Ben Voigt
Apr 30 at 3:18
add a comment |
2
$begingroup$
Looks like an 'OR' gate to me... but maybe I just don't understand how you intend for those switches to work (that's a problem with your answer -- you didn't even try to describe their behavior)
$endgroup$
– Ben Voigt
Apr 30 at 3:18
2
2
$begingroup$
Looks like an 'OR' gate to me... but maybe I just don't understand how you intend for those switches to work (that's a problem with your answer -- you didn't even try to describe their behavior)
$endgroup$
– Ben Voigt
Apr 30 at 3:18
$begingroup$
Looks like an 'OR' gate to me... but maybe I just don't understand how you intend for those switches to work (that's a problem with your answer -- you didn't even try to describe their behavior)
$endgroup$
– Ben Voigt
Apr 30 at 3:18
add a comment |
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The source impedance of the switch is 0 while in normal logic it is <=50 Ohms so the load impedance being much higher permits many loads to applied without significant change in voltage. For TTL, the limit was 10 units of load. But for static CMOS , the limit depends on the equivalent input capacitance and current limit of the switch as this affects rise/fall time. T=RC
$endgroup$
– Sunnyskyguy EE75
Apr 30 at 1:02
$begingroup$
"I see that when the two switches are closed, there is a path from V+ to ground, and that current will flow to ground. But there's also a path from V+ to Q,". No, there is only 1 path, V+ to ground, Q is a point on that path. And, when the switches are closed, Q is at the same potential as ground.
$endgroup$
– Glen Yates
Apr 30 at 15:13