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What is this Amiga 1200 mod?
What are the Amiga 1200 timing fixes?HxC floppy emulator on Amiga 1200, second virtual drive disappears after rebootWhy does my Macintosh SE FDHD only see 2 of the 4 megabytes of RAM?Will using a clockport RTC card on an Amiga 1200 clash with the RTC on an accelerator card?Is it possible to adapt a standard PC floppy drive to work in an IBM PS/2?Which ports are which on this Soviet ZX Spectrum clone?Can't get the AY-3-8913 sound chip to work with my z80 (added schematic)Smallest/Simplest, modern pure relay computer with at least 4-bits data wordsLargest practical motherboard for early computers“Unexpected interrupt in protected mode” after installing 486 DX2
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I got an Amiga 1200 off ebay and it works great, board looks perfect, no leakage, no bad traces, nothing, and yet I have this mysterious mod I've never seen before. Does anyone know what it is?
hardware amiga-1200
edited Jun 8 at 19:34
RonJohn
2581 silver badge6 bronze badges
asked Jun 8 at 10:33
Bartek MalyszBartek Malysz
2768 bronze badges
add a comment |
I got an Amiga 1200 off ebay and it works great, board looks perfect, no leakage, no bad traces, nothing, and yet I have this mysterious mod I've never seen before. Does anyone know what it is?
hardware amiga-1200
edited Jun 8 at 19:34
RonJohn
2581 silver badge6 bronze badges
asked Jun 8 at 10:33
Bartek MalyszBartek Malysz
2768 bronze badges
add a comment |
I got an Amiga 1200 off ebay and it works great, board looks perfect, no leakage, no bad traces, nothing, and yet I have this mysterious mod I've never seen before. Does anyone know what it is?
hardware amiga-1200
edited Jun 8 at 19:34
RonJohn
2581 silver badge6 bronze badges
asked Jun 8 at 10:33
Bartek MalyszBartek Malysz
2768 bronze badges
I got an Amiga 1200 off ebay and it works great, board looks perfect, no leakage, no bad traces, nothing, and yet I have this mysterious mod I've never seen before. Does anyone know what it is?
hardware amiga-1200
hardware amiga-1200
edited Jun 8 at 19:34
RonJohn
2581 silver badge6 bronze badges
asked Jun 8 at 10:33
Bartek MalyszBartek Malysz
2768 bronze badges
edited Jun 8 at 19:34
RonJohn
2581 silver badge6 bronze badges
asked Jun 8 at 10:33
Bartek MalyszBartek Malysz
2768 bronze badges
edited Jun 8 at 19:34
RonJohn
2581 silver badge6 bronze badges
edited Jun 8 at 19:34
RonJohn
2581 silver badge6 bronze badges
edited Jun 8 at 19:34
RonJohn
2581 silver badge6 bronze badges
2581 silver badge6 bronze badges
asked Jun 8 at 10:33
Bartek MalyszBartek Malysz
2768 bronze badges
asked Jun 8 at 10:33
Bartek MalyszBartek Malysz
2768 bronze badges
asked Jun 8 at 10:33
Bartek MalyszBartek Malysz
2768 bronze badges
2768 bronze badges
add a comment |
add a comment |
1 Answer
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I believe it is to clean the weak CCK clock signal coming from Alice to Budgie.
PCB rev 1.d4 and 2b should have this.
It is on the R2 schematic (http://www.amigawiki.de/dnl/schematics/A1200_R2.pdf) - search for "BUDGIE BLUES" and check pin 36 (CCK).
I think U37 ("TI 231 JFA HC08" in your photo) is a quad positive-or (74F32 / SN74S32) which is serving as the buffer.
answered Jun 8 at 13:01
matjamatja
2161 silver badge3 bronze badges
2
Are you able to explain what that's for? in other words why should a clock be cleaned
– Wilson
Jun 8 at 19:51
3
@Wilson because the clock signal was marginal due to poor layout, high fanout, incorrectly specced / manufactured driver, etc. Clock buffering is a standard part of digital design, this after-the-fact rework was needed because the required buffer here was overlooked / omittted during initial design.
– madscientist159
Jun 8 at 20:18
add a comment |
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1 Answer
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1 Answer
1
active
oldest
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active
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votes
I believe it is to clean the weak CCK clock signal coming from Alice to Budgie.
PCB rev 1.d4 and 2b should have this.
It is on the R2 schematic (http://www.amigawiki.de/dnl/schematics/A1200_R2.pdf) - search for "BUDGIE BLUES" and check pin 36 (CCK).
I think U37 ("TI 231 JFA HC08" in your photo) is a quad positive-or (74F32 / SN74S32) which is serving as the buffer.
answered Jun 8 at 13:01
matjamatja
2161 silver badge3 bronze badges
2
Are you able to explain what that's for? in other words why should a clock be cleaned
– Wilson
Jun 8 at 19:51
3
@Wilson because the clock signal was marginal due to poor layout, high fanout, incorrectly specced / manufactured driver, etc. Clock buffering is a standard part of digital design, this after-the-fact rework was needed because the required buffer here was overlooked / omittted during initial design.
– madscientist159
Jun 8 at 20:18
add a comment |
I believe it is to clean the weak CCK clock signal coming from Alice to Budgie.
PCB rev 1.d4 and 2b should have this.
It is on the R2 schematic (http://www.amigawiki.de/dnl/schematics/A1200_R2.pdf) - search for "BUDGIE BLUES" and check pin 36 (CCK).
I think U37 ("TI 231 JFA HC08" in your photo) is a quad positive-or (74F32 / SN74S32) which is serving as the buffer.
answered Jun 8 at 13:01
matjamatja
2161 silver badge3 bronze badges
2
Are you able to explain what that's for? in other words why should a clock be cleaned
– Wilson
Jun 8 at 19:51
3
@Wilson because the clock signal was marginal due to poor layout, high fanout, incorrectly specced / manufactured driver, etc. Clock buffering is a standard part of digital design, this after-the-fact rework was needed because the required buffer here was overlooked / omittted during initial design.
– madscientist159
Jun 8 at 20:18
add a comment |
I believe it is to clean the weak CCK clock signal coming from Alice to Budgie.
PCB rev 1.d4 and 2b should have this.
It is on the R2 schematic (http://www.amigawiki.de/dnl/schematics/A1200_R2.pdf) - search for "BUDGIE BLUES" and check pin 36 (CCK).
I think U37 ("TI 231 JFA HC08" in your photo) is a quad positive-or (74F32 / SN74S32) which is serving as the buffer.
answered Jun 8 at 13:01
matjamatja
2161 silver badge3 bronze badges
I believe it is to clean the weak CCK clock signal coming from Alice to Budgie.
PCB rev 1.d4 and 2b should have this.
It is on the R2 schematic (http://www.amigawiki.de/dnl/schematics/A1200_R2.pdf) - search for "BUDGIE BLUES" and check pin 36 (CCK).
I think U37 ("TI 231 JFA HC08" in your photo) is a quad positive-or (74F32 / SN74S32) which is serving as the buffer.
answered Jun 8 at 13:01
matjamatja
2161 silver badge3 bronze badges
answered Jun 8 at 13:01
matjamatja
2161 silver badge3 bronze badges
answered Jun 8 at 13:01
matjamatja
2161 silver badge3 bronze badges
answered Jun 8 at 13:01
matjamatja
2161 silver badge3 bronze badges
2161 silver badge3 bronze badges
2
Are you able to explain what that's for? in other words why should a clock be cleaned
– Wilson
Jun 8 at 19:51
3
@Wilson because the clock signal was marginal due to poor layout, high fanout, incorrectly specced / manufactured driver, etc. Clock buffering is a standard part of digital design, this after-the-fact rework was needed because the required buffer here was overlooked / omittted during initial design.
– madscientist159
Jun 8 at 20:18
add a comment |
2
Are you able to explain what that's for? in other words why should a clock be cleaned
– Wilson
Jun 8 at 19:51
3
@Wilson because the clock signal was marginal due to poor layout, high fanout, incorrectly specced / manufactured driver, etc. Clock buffering is a standard part of digital design, this after-the-fact rework was needed because the required buffer here was overlooked / omittted during initial design.
– madscientist159
Jun 8 at 20:18
2
2
Are you able to explain what that's for? in other words why should a clock be cleaned
– Wilson
Jun 8 at 19:51
Are you able to explain what that's for? in other words why should a clock be cleaned
– Wilson
Jun 8 at 19:51
3
3
@Wilson because the clock signal was marginal due to poor layout, high fanout, incorrectly specced / manufactured driver, etc. Clock buffering is a standard part of digital design, this after-the-fact rework was needed because the required buffer here was overlooked / omittted during initial design.
– madscientist159
Jun 8 at 20:18
@Wilson because the clock signal was marginal due to poor layout, high fanout, incorrectly specced / manufactured driver, etc. Clock buffering is a standard part of digital design, this after-the-fact rework was needed because the required buffer here was overlooked / omittted during initial design.
– madscientist159
Jun 8 at 20:18
add a comment |
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